This invention relates to improvements in digital processing circuitry for performing analog-to-digital (A/D) conversion of a bipolar analog signal, such circuitry being of the type which employs the technique of feedback-type, successive ranging. By this technique, a circuit provides a digital number output word containing a total range of M bits, by iterative use of a fast, internal, A/D converter circuit which produces a subrange conversion word of a fewer number of bits, S. The invention is of particular utility in applications for which mass reproducible circuit constructions are employed. Such mass reproducible circuit constructions, such as integrated circuits, are limited in linearity, fidelity, and accuracy.
There has been a continuing effort to achieve higher speeds of conversion. A high priority motivation behind this effort is the application of A/D conversion circuits to the performance of complex analysis of radar signals. In this application, higher conversion speeds are desired in order to more thoroughly analyze the signal within real-time constraints, and to build the equipment to be compatible with cost constraints and size of the equipment constraints.
One approach to improving conversion speeds stems from recognition of the importance of efficient utilization of the flip-flop stage capacity of the internal, subranging, A/D converter. This is illustrated in U.S. Pat. No. 3,483,550 which employs a bipolar subranging A/D converter. The bipolar subranging A/D converter therein does not require use of any of its A/D flip-flop stages to process the polarity sign information. Instead, the polarity sign information is manipulated by auxiliary logic. In turn, the auxiliary logic is operatively associated with the arithmetic circuitry which combines the results of iterative subrange conversions. The one flip-flop stage of the subranging A/D converter which becomes available for quantitative manipulations by this technique picks up one extra bit of representation for each iteration, thereby achieving faster conversions. However, the approach of manipulating the polarity sign by the auxiliary logic perpetuates a need for the generally slower bipolar, addition and subtraction arithmetic circuitry.
Another approach to improving conversion speeds stems from recognition of the importance of using arithmetic circuit structures which have fast settling times. This is illustrated in U.S. Pat. Nos. 3,541,315 and 3,581,304. In those patents, bias is fed into the analog subtractor at the point at which the feedback is returned. This bias is chosen to maintain a relationship by which the feedback is smaller than the input signal. The result which this provides is that every successive subrange conversion may be added to the preceding subrange. It permits use of unipolar, add-only, arithmetic circuitry which affords the advantage of its inherently faster settling times.
Prior to the present invention, there has been no instance of an A/D conversion circuit which avoids the slowness of bipolar, addition and subtraction circuitry while obviating the problem of inefficient utilization of the flip-flop stage capacity of the subranging A/D converter and which avoids the slowness of bipolar, addition and subtraction circuitry.